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ADC0804S030/040/050 single 8 bits adc, up to 30 mhz, 40 mhz or 50 mhz rev. 03 ? 2 july 2012 product data sheet 1. general description the adc0806030/040/050 are a family of 8-bi t high-speed, low-power analog-to-digital converters (adc) for professional video and other applications. it converts the analog input signal into 8-bit binary coded digital si gnals at a maximum sampling rate of 50 mhz. all digital inputs and outputs are transistor-t ransistor logic (ttl) and cmos compatible, although a low-level sine wave clock input signal can also be used. the device requires an external source to drive its reference ladder. if the application r equires that the reference is driven via inte rnal sources, idt recommends you use one of the adc1003s030/040/050 family. 2. features ? 8-bit resolution ? sa mpling rate up to 50 mhz ? dc sampling allowed ? one clock cycle conversion only ? high signal-to-noise ratio over a large analog input frequency range (7.8 effective bits at 4.43 mhz full-scale input at f clk = 40 mhz) ? no missing cod es guaranteed ? in-r ange (ir) cmos output ? ttl and cmos levels compatible digital inputs ? 3 v to 5 v cmos digital outputs ? low-lev el ac clock input signal allowed ? exte rnal reference voltage regulator ? powe r dissipation only 175 mw (typical) ? l ow analog input capacitance, no buffer amplifier required ? no samp le-and-hold circuit required 3. applications ? video data digitizing ? radar ? t ransient signal analysis ? ?? m odulators ? medical imaging ? bar code scanner ? global pos itioning system (gps) receiver
ADC0804S030_040_050_3 ? idt 2012. all rights reserved. product data sheet rev. 03 ? 2 july 2012 2 of 18 integrated device technology ADC0804S030/040/050 single 8 bits adc, up to 30 mhz, 40 mhz or 50 mhz ? cellular base stations 4. quick reference data table 1. quick reference data v cca = v3 to v4 = 4.75 v to 5.25 v; v ccd = v11 to v12 and v28 to v27 = 4.75 v to 5.25 v; v cco = v13 to v14 = 3.0 v to 5.25 v; agnd and dgnd shorted together; t amb = 0 ? c to 70 ? c; typical values measured at v cca = v ccd = 5 v and v cco = 3.3 v, v i(a)(p-p) = 2.0 v; c l = 15 pf and t amb = 25 ? c; unless otherwise specified. symbol parameter conditions min typ max unit v cca analog supply voltage 4.75 5.0 5.25 v v ccd digital supply voltage 4.75 5.0 5.25 v v cco output supply voltage 3.0 3.3 5.25 v i cca analog supply current - 18 24 ma i ccd digital supply current - 16 21 ma i cco output supply current f clk = 40 mhz; ramp input - 1 2 ma inl integral non-linearity f clk = 40 mhz ra mp input - ? 0.2 ? 0.5 lsb dnl differential non-linearity f clk = 40 mhz ra mp input - ? 0.12 ? 0.22 lsb f clk(max) maximum clock frequency ADC0804S030ts 30 - - mhz adc0804s040ts 40 - - mhz adc0804s050ts 50 - - mhz p tot total power dissipation f clk = 40 mhz; ra mp input - 175 247 mw 5. ordering information table 2. ordering information type number package sampling frequency (mhz) name description version ADC0804S030ts ssop28 plastic shrink small outline package; 28 leads; body width 5.3 mm sot341-1 30 adc0804s040ts ssop28 plastic shrink small outline package; 28 leads; body width 5.3 mm sot341-1 40 adc0804s050ts ssop28 plastic shrink small outline package; 28 leads; body width 5.3 mm sot341-1 50
ADC0804S030_040_050_3 ? idt 2012. all rights reserved. product data sheet rev. 03 ? 2 july 2012 3 of 18 integrated device technology ADC0804S030/040/050 single 8 bits adc, up to 30 mhz, 40 mhz or 50 mhz 6. block diagram 12 dgnd2 6 8 r lad 7 9 rb rm rt vi 11 v ccd2 3 26 v cca 21 22 23 24 20 d2 d3 d4 d5 d6 19 18 25 2 d1 d0 d7 in-range latch cmos outputs latches clock driver 014aaa550 1 clk 10 oe tc ADC0804S030 13 v cco 4 agnd analog ground digital ground digital ground 27 dgnd1 14 ognd output ground analog voltage input data outputs lsb msb 28 v ccd1 ir output analog - to - digital converter cmos output fig 1. block diagram
ADC0804S030_040_050_3 ? idt 2012. all rights reserved. product data sheet rev. 03 ? 2 july 2012 4 of 18 integrated device technology ADC0804S030/040/050 single 8 bits adc, up to 30 mhz, 40 mhz or 50 mhz 7. pinning information 7.1 pinning adc0804s 030ts clk v ccd1 tc dgnd1 v cca ir agnd d7 n.c. d6 rb d5 rm d4 vi d3 rt d2 oe d1 v ccd2 d0 dgnd2 n.c. v cco n.c. ognd n.c. 014aaa551 1 2 3 4 5 6 7 8 9 10 11 12 13 14 16 15 18 17 20 19 22 21 24 23 26 25 28 27 fig 2. pin configuration 7.2 pin description table 3. pin description symbol pin description clk 1 clock input tc 2 two?s complement input (active low) v cca 3 analog supply voltage (5 v) agnd 4 analog ground n.c. 5 not connected rb 6 reference voltage bottom input rm 7 reference voltage middle vi 8 analog input voltage rt 9 reference voltage top input oe 10 output enable input (cmos level input, active low) v ccd2 11 digital supply voltage 2 (5 v) dgnd2 12 digital ground 2 v cco 13 supply voltage for output stages (3 v to 5 v) ognd 14 output ground n.c. 15 not connected n.c. 16 not connected n.c. 17 not connected d0 18 data output; bit 0 (least significant bit (lsb)) d1 19 data output; bit 1
ADC0804S030_040_050_3 ? idt 2012. all rights reserved. product data sheet rev. 03 ? 2 july 2012 5 of 18 integrated device technology ADC0804S030/040/050 single 8 bits adc, up to 30 mhz, 40 mhz or 50 mhz 8. limiting values table 4. limiting values in accordance with the absolute maximum rating system (iec 60134). symbol parameter conditions min max unit v cca analog supply voltage [1] ? 0.3 +7.0 v v ccd digital supply voltage [1] ? 0.3 +7.0 v v cco output supply voltage [1] ? 0.3 +7.0 v ? v cc supply voltage difference v cca ? v ccd ? 1.0 +1.0 v v ccd ? v cco ? 1.0 +4.0 v v cca ? v cco ? 1.0 +4.0 v v i input voltage referenced to agnd ? 0.3 +7.0 v v i(clk)(p-p) peak-to-peak clock input voltage referenced to dgnd - v ccd v i o output current - 10 ma t stg storage temperature ? 55 +150 ?c t amb ambient temperature ? 40 +85 ?c t j junction temperature - 150 ?c [1] the supply voltages v cca , v ccd and v cco may have any value between ?0.3 v and +7.0 v provided that the supply volt age differences ? v cc are respected. 9. thermal characteristics table 5. thermal characteristics symbol parameter conditions typ unit r th(j-a) thermal resistance from junction to ambient in free air 110 k/w d2 20 data output; bit 2 d3 21 data output; bit 3 d4 22 data output; bit 4 d5 23 data output; bit 5 d6 24 data output; bit 6 d7 25 data output; bit 7 (most significant bit (msb)) ir 26 in-range data output dgnd1 27 digital ground 1 v ccd1 28 digital supply voltage 1 (5 v) table 3. pin description ?continued symbol pin description
ADC0804S030_040_050_3 ? idt 2012. all rights reserved. product data sheet rev. 03 ? 2 july 2012 6 of 18 integrated device technology ADC0804S030/040/050 single 8 bits adc, up to 30 mhz, 40 mhz or 50 mhz 10. characteristics table 6. characteristics v cca = v3 to v4 = 4.75 v to 5.25 v; v ccd = v11 to v12 and v28 to v27 = 4.75 v to 5.25 v; v cco = v13 to v14 = 3.0 v to 5.25 v; agnd and dgnd shor ted together; t amb = 0 q c to 70 q c; typical values measured at v cca = v ccd = 5 v and v cco = 3.3 v, v i(a)(p-p) = 2.0 v; c l = 15 pf and t amb = 25 q c; unless otherwise specified. symbol parameter conditions min typ max unit supplies v cca analog supply voltage 4.75 5.0 5.25 v v ccd digital supply voltage 4.75 5.0 5.25 v v cco output supply voltage 3.0 3.3 5.25 v ' v cc supply voltage difference v cca v ccd 0.20 - +0.20 v v cca v cco 0.20 - +2.25 v v ccd v cco 0.20 - +2.25 v i cca analog supply current - 18 24 ma i ccd digital supply current - 16 21 ma i cco output supply current f clk = 40 mhz; ramp input - 1 2 ma p tot total power dissipation f clk = 40 mhz; ramp input - 175 247 mw inputs clock input clk (referenced to dgnd) [1] v il low-level input voltage 0 - 0.8 v v ih high-level input voltage 2 - v ccd v i il low-level input current v clk = 0.8 v 1 - +1 p a i ih high-level input current v clk = 2 v - 2 10 p a z i input impedance f clk = 40 mhz - 2 - k : c i input capacitance - 2 - pf oe and tc (referenced to dgnd); see ta b l e 8 v il low-level input voltage 0 - 0.8 v v ih high-level input voltage 2 - v ccd v i il low-level input current v il = 0.8 v 1 - - p a i ih high-level input current v ih = 2.0 v - - 1 p a vi (analog input voltage referenced to agnd) i il low-level input current v i = v rb = 1.3 v - 0 - p a i ih high-level input current v i = v rt = 3.67 v - 35 - p a z i input impedance f i = 4.43 mhz - 8 - k : c i input capacitance - 5 - pf reference voltages for the resistor ladder; see table 7 v rb voltage on pin rb 1.2 1.3 2.45 v v rt voltage on pin rt 3.2 3.67 v cca 0.8 v
ADC0804S030_040_050_3 ? idt 2012. all rights reserved. product data sheet rev. 03 ? 2 july 2012 7 of 18 integrated device technology ADC0804S030/040/050 single 8 bits adc, up to 30 mhz, 40 mhz or 50 mhz v ref(dif) differential reference voltage v rt v rb 2.0 2.37 3.0 v i ref reference current v rt v rb = 2.37 v - 9.7 - ma r lad ladder resistance - 245 - : tc rlad ladder resistor temperature coefficient - 456 - m : /k v offset offset voltage bottom; v rt v rb = 2.37 v [2] - 175 - mv top; v rt v rb = 2.37 v [2] - 175 - mv v i(a)(p-p) peak-to-peak analog input voltage [3] 1.7 2.02 2.55 v digital outputs d7 to d0 and ir (referenced to ognd) v ol low-level output voltage i ol = 1 ma 0 - 0.5 v v oh high-level output voltage i oh = 1 ma v cco 0.5 - v cco v i o output current in 3-state mode; 0.5 v < v o < v cco 20 - +20 p a switching characteristics; clock input clk; see figure 4 [1] f clk(max) maximum clock frequency ADC0804S030ts 30 - - mhz adc0804s040ts 40 - - mhz adc0804s050ts 50 - - mhz t w(clk)h high clock pulse width full effective bandwidth 8.5 - - ns t w(clk)l low clock pulse width full effective bandwidth 5.5 - - ns analog signal processing linearity inl integral non-linearity f clk = 40 mhz; ramp input - r 0.2 r 0.5 lsb dnl differential non-linearity f clk = 40 mhz; ramp input - r 0.12 r 0.22 lsb e offset offset error middle code; v rb = 1.3 v; v rt = 3.67 v - r 0.25 - lsb e g gain error from device to device; v rb = 1.3 v; v rt = 3.67 v [4] - r 0.1 - % bandwidth (f clk = 40 mhz) b bandwidth full-scale sine wave [5] - 15 - mhz 75 % full-scale sine wave - 20 - mhz small signal at mid-scale; v i = r 10 lsb at code 512 - 350 - mhz t s(lh) low to high settling time full-scale square wave; see figure 6 [6] - 1.5 3.0 ns t s(hl) high to low settling time - 1.5 3.0 ns table 6. characteristics v cca = v3 to v4 = 4.75 v to 5.25 v; v ccd = v11 to v12 and v28 to v27 = 4.75 v to 5.25 v; v cco = v13 to v14 = 3.0 v to 5.25 v; agnd and dgnd shor ted together; t amb = 0 q c to 70 q c; typical values measured at v cca = v ccd = 5 v and v cco = 3.3 v, v i(a)(p-p) = 2.0 v; c l = 15 pf and t amb = 25 q c; unless otherwise specified. symbol parameter conditions min typ max unit
ADC0804S030_040_050_3 ? idt 2012. all rights reserved. product data sheet rev. 03 ? 2 july 2012 8 of 18 integrated device technology ADC0804S030/040/050 single 8 bits adc, up to 30 mhz, 40 mhz or 50 mhz harmonics (f clk = 40 mhz); see figure 7 and 8 d 1h first harmonic level f i = 4.43 mhz - - 0 db d 2h second harmonic level f i = 4.43 mhz - 75 65 db d 3h third harmonic level f i = 4.43 mhz - 72 65 db thd total harmonic distortion f i = 4.43 mhz - 65 - db signal-to-noise ratio; see figure 7 and 8 [7] s/n signal-to-noise ratio full scale; without harmonics; f clk = 40 mhz; f i = 4.43 mhz 46 49 - db effective number of bits [7] enob effective number of bits ADC0804S030ts (f clk = 30 mhz) f i = 4.43 mhz - 7.8 - bits f i = 7.5 mhz - 7.8 - bits adc0804s040ts (f clk = 40 mhz) f i = 4.43 mhz - 7.8 - bits f i = 7.5 mhz - 7.8 - bits f i = 10 mhz - 7.8 - bits f i = 15 mhz - 7.4 - bits adc0804s050ts (f clk = 50 mhz) f i = 4.43 mhz - 7.8 - bits f i = 7.5 mhz - 7.8 - bits f i = 10 mhz - 7.8 - bits f i = 15 mhz - 7.3 - bits two-tone intermodulation [8] d im intermodulation suppression f clk = 40 mhz - 69 - db bit error rate ber bit error rate f clk = 40 mhz; f i = 4.43 mhz; v i = r 16 lsb at code 512 - 10 13 - times/ samples differential gain [9] g dif differential gain f clk = 40 mhz; pal modulated ramp - 0.8 - % table 6. characteristics v cca = v3 to v4 = 4.75 v to 5.25 v; v ccd = v11 to v12 and v28 to v27 = 4.75 v to 5.25 v; v cco = v13 to v14 = 3.0 v to 5.25 v; agnd and dgnd shor ted together; t amb = 0 q c to 70 q c; typical values measured at v cca = v ccd = 5 v and v cco = 3.3 v, v i(a)(p-p) = 2.0 v; c l = 15 pf and t amb = 25 q c; unless otherwise specified. symbol parameter conditions min typ max unit
ADC0804S030_040_050_3 ? idt 2012. all rights reserved. product data sheet rev. 03 ? 2 july 2012 9 of 18 integrated device technology ADC0804S030/040/050 single 8 bits adc, up to 30 mhz, 40 mhz or 50 mhz [1] in addition to a good layout of the digital and analog ground, it is recommended that the rise and fall times of the clock must not be less than 0.5 ns. [2] analog input voltages producing code 0 up to and including code 255: a) v offset bottom is the difference between the analog input which produces data equal to 00 and the reference voltage on pin rb (v rb ) at t amb = 25 ? c. b) v offset top is the difference between the reference voltage on pin rt (v rt ) and the analog input which produces data outputs equal to code 255 at t amb = 25 ? c . [3] to ensure the optimum linearity performance of such a converte r architecture the lower and upper extremities of the converte r reference resistor ladder are connected to pins rb and rt via offset resistors r ob and r ot as shown in figure 3. a) the current flowing into the resistor ladder is i v rt v rb ? r ob r l r ot ++ --------------------------------------- = and the full-scale input range at the converter, to cover code 0 to 255 is v i r l i l ? r l r ob r l r ot ++ --------------------------------------- v rt v rb + ?? ? 0.852 v rt v rb ? ?? ? == = b) since r l , r ob and r ot have similar behavior with respect to process and temperature variation, the ratio r l r ob r l r ot ++ --------------------------------------- will be kept reasonably constant from devic e to device. co nsequently, the variation of the output codes at a given input voltag e depends mainly on the difference v rt ? v rb and its variation with temperature and supply voltage. when several adcs are connected in parallel and fed with the same reference source, the matching between each of them is optimized. [4] e g v 1023 v 0 ? ?? v ip p ? ?? ? v ip p ? ?? ------------------------------------------------------ - 100 ? = [5] the analog bandwidth is defined as the maximum input sine wave frequency which can be applied to the device. no glitches gre ater than 0.5 lsb, neither any significant attenuati on are observed in the reconstructed signal. [6] the analog input settling time is the minimum time required for the input signal to be stabilized after a sharp full-scale i nput (square wave signal) in order to sample the signal and obtain correct output data. differential phase [9] ? dif differential phase f clk = 40 mhz; pal modulated ramp - 0.4 - deg timing (f clk = 40 mhz; c i = 15 pf); see figure 4 [10] t d(s) sampling delay time - 3 - ns t h(o) output hold time 4 - - ns t d(o) output delay time v cco = 4.75 v - 10 13 ns v cco = 3.15 v - 12 15 ns c l load capacitance - - 15 pf 3-state output delay times; see figure 5 t dzh float to active high delay time - 5.5 8.5 ns t dzl float to active low delay time - 12 15 ns t dhz active high to float delay time - 19 24 ns t dlz active low to float delay time - 12 15 ns table 6. characteristics v cca = v3 to v4 = 4.75 v to 5.25 v; v ccd = v11 to v12 and v28 to v27 = 4.75 v to 5.25 v; v cco = v13 to v14 = 3.0 v to 5.25 v; agnd and dgnd shor ted together; t amb = 0 ? ? ? symbol parameter conditions min typ max unit
ADC0804S030_040_050_3 ? idt 2012. all rights reserved. product data sheet rev. 03 ? 2 july 2012 10 of 18 integrated device technology ADC0804S030/040/050 single 8 bits adc, up to 30 mhz, 40 mhz or 50 mhz [7] effective bits are obtained via a fast fourier transform (fft) treatment taking 8000 acquisi tion points per equivalent funda mental period. the calculation takes into acc ount all harmonics and noise up to half th e clock frequency (nyqui st frequency). conversi on to signal-to-noise-and-distortion (sinad) ratio: sinad = enob ? 6.02 + 1.76 db. [8] intermodulation measured relative to either tone with analog inp ut frequencies of 4.43 mhz and 4.53 mhz. the two input signa ls have the same amplitude and the total amplitude of both si gnals provides full-sca le to the converter. [9] measurement carried out using video analyzer vm700a, where the video analog sig nal is reconstr ucted through a digital-to-ana log converter. [10] output data acquisition: the output data is available af ter the maximum delay time of t d(0) . for 50 mhz version idt recommend the lowest possible output load. 014aaa555 rt rb rm r lad r ot r l r l r l r l i l r ob code 255 code 0 fig 3. explanation of table 6 table note 3 11. additional information relating to table 6 table 7. output coding and input voltage (typical values; referenced to agnd, v rb = 1.3 v, v rt = 3.67 v) code v i(a)(p-p) (v) ir binary outputs d7 to d0 two?s complement outputs d7 to d0 underflow < 1.475 0 0000 0000 10 0000 00 0 1.475 1 0000 0000 10 0000 00 1 - 1 0000 0001 10 0000 01 ? - ? ? ? 254 - 1 1111 1110 01 1111 10 255 3.495 1 1111 1111 01 1111 11 overflow > 3.495 0 1111 1111 01 1111 11
ADC0804S030_040_050_3 ? idt 2012. all rights reserved. product data sheet rev. 03 ? 2 july 2012 11 of 18 integrated device technology ADC0804S030/040/050 single 8 bits adc, up to 30 mhz, 40 mhz or 50 mhz table 8. mode selection tc oe d7 to d0 ir x 1 high impedance high impedance 0 0 active; two?s complement active 1 0 active; binary active 014aaa556 clk vi data n ? 2 data d0 to d7 data n ? 1 data n data n + 1 sample n + 2 sample n + 1 v cco sample n sample n + 2 sample n + 1 sample n t w(clk)h t w(clk)l t d(s) t d(o) t h(o) 50 % 0 v v cco 50 % 0 v fig 4. timing diagram
ADC0804S030_040_050_3 ? idt 2012. all rights reserved. product data sheet rev. 03 ? 2 july 2012 12 of 18 integrated device technology ADC0804S030/040/050 single 8 bits adc, up to 30 mhz, 40 mhz or 50 mhz low high high low ADC0804S030 v ccd v ccd s1 oe oe output data output data 10 % 50 % 50 % 90 % 50 % t dlz t dzl t dhz t dzh 15 pf 3.3 k s1 test v ccd t dlz v ccd t dzl dgnd t dzh t dhz dgnd 014aaa552 frequency on pin oe = 100 khz fig 5. timing diagram and test conditions of 3-state output delay time 014aaa400 code 255 code 0 50 % 50 % clk vi t s(lh) t s(hl) 50 % 50 % 2 ns 2 ns 0.5 ns 0.5 ns fig 6. analog input settling time diagram
ADC0804S030_040_050_3 ? idt 2012. all rights reserved. product data sheet rev. 03 ? 2 july 2012 13 of 18 integrated device technology ADC0804S030/040/050 single 8 bits adc, up to 30 mhz, 40 mhz or 50 mhz 014aaa328 ?60 ?100 ?20 +20 amplitude (db) ?140 f (mhz) 0 20.0 15.0 5.00 10.0 effective bits: 7.84; thd = ?71.8 db. harmonic levels (db): 2nd = ?83.1 9; 3rd = ? 78.09; 4th = ? 78.72; 5th = ? 78.33; 6th = ?77.55. fig 7. typical fast fourier transform (f clk = 40 mhz; f i = 4.43 mhz) 0 f (mhz) 20.0 25.0 15.0 5.0 10.0 014aaa329 ?60 ?100 ?20 +20 amplitude (db) ?140 effective bits: 7.79; thd = ?62.96 db. harmonic levels (db): 2nd = ? 71.38; 3rd = ? 71.54; 4th = ? 74.14; 5th = ? 65.15; 6th = ?77.16. fig 8. typical fast fourier transform (f clk = 50 mhz; f i = 10 mhz)
ADC0804S030_040_050_3 ? idt 2012. all rights reserved. product data sheet rev. 03 ? 2 july 2012 14 of 18 integrated device technology ADC0804S030/040/050 single 8 bits adc, up to 30 mhz, 40 mhz or 50 mhz 014aaa557 v cco d7 to d0 ir ognd v cca vi agnd 014aaa526 fig 9. cmos data and in-range outputs fig 10. analog inputs 014aaa553 v cco ognd oe tc v cca rt rm rb agnd 014aaa331 r l r l r l r l fig 11. oe and tc input fig 12. rb, rm and rt v ccd clk 1.5 v dgnd 014aaa399 fig 13. clk input
ADC0804S030_040_050_3 ? idt 2012. all rights reserved. product data sheet rev. 03 ? 2 july 2012 15 of 18 integrated device technology ADC0804S030/040/050 single 8 bits adc, up to 30 mhz, 40 mhz or 50 mhz 12. application information ADC0804S030 clk v ccd1 tc dgnd1 v cca ir agnd d7 n.c. d6 rb (1) d5 rm (1) d4 vi d3 rt (1) d2 oe d1 v ccd2 d0 dgnd2 n.c. v cco n.c. ognd n.c. (2) 014aaa554 1 2 3 4 5 6 7 8 9 10 11 12 13 14 16 15 18 17 20 19 22 21 24 23 26 25 28 27 100 nf 100 nf 100 nf 100 nf 100 nf 100 nf 100 nf (3) (3) (3) (3) agnd agnd agnd the analog and digital supplies shoul d be separated and well decoupled a user manual is available that describes the demonstration board that uses the version ADC0804S030/040/050/ family with an application environment. (1) rb, rm and rt are decoupled to agnd. (2) pin 15 may be connected to dgnd in or der to prevent noise influence. (3) decoupling capacitor for supplies; must be placed close to the de vice. fig 14. application diagram 12.1 alternative parts the following alternative parts are also available: table 9. alternative parts type number description sampling frequency adc1004s030 single 10 bits adc [1] 30 mhz adc1004s040 single 10 bits adc [1] 40 mhz adc1004s050 single 10 bits adc [1] 50 mhz adc1003s030 single 10 bits adc [1] 30 mhz, with inte rnal reference regulator adc1003s040 single 10 bits adc [1] 40 mhz, with inte rnal reference regulator adc1003s050 single 10 bits adc [1] 50 mhz, with inte rnal reference regulator adc1005s060 single 10 bits adc [1] 60 mhz [1] pin to pin compatible
ADC0804S030_040_050_3 ? idt 2012. all rights reserved. product data sheet rev. 03 ? 2 july 2012 16 of 18 integrated device technology ADC0804S030/040/050 single 8 bits adc, up to 30 mhz, 40 mhz or 50 mhz 13. package outline unit a 1 a 2 a 3 b p cd (1) e (1) (1) eh e ll p qz ywv references outline version european projection issue date iec jedec jeita mm 0.21 0.05 1.80 1.65 0.38 0.25 0.20 0.09 10.4 10.0 5.4 5.2 0.65 1.25 7.9 7.6 0.9 0.7 1.1 0.7 8 0 o o 0.13 0.1 0.2 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.2 mm maximum per side are not included. 1.03 0.63 sot341-1 mo-150 99-12-27 03-02-19 x w m a a 1 a 2 b p d h e l p q detail x e z e c l v m a (a ) 3 a 11 4 28 15 0.25 y pin 1 index 0 2.5 5 mm scale ssop28: plastic shrink small outline package; 28 leads; body width 5.3 mm sot341-1 a max. 2 fig 15. sot341-1 (ssop28)
ADC0804S030_040_050_3 ? idt 2012. all rights reserved. product data sheet rev. 03 ? 2 july 2012 17 of 18 integrated device technology ADC0804S030/040/050 single 8 bits adc, up to 30 mhz, 40 mhz or 50 mhz 14. revision history table 10. revision history document id release date data sheet status change notice supersedes ADC0804S030_040_050_3 20120702 product data sheet - ADC0804S030_040_050_2 ADC0804S030_040_050_2 20080814 product data sheet - ADC0804S030_040_050_1 modifications: paragraph added to section ? 1. corrections to descriptions of rows rb and rm in table ? 3. corrections to table ? 6. corrections to figure ? 9, 10 and 12. ADC0804S030_040_050_1 20080616 product data sheet - - 15. contact information for more information or sales office addresses, please visit: http://www.idt.com
ADC0804S030_040_050_3 ? idt 2012. all rights reserved. product data sheet rev. 03 ? 2 july 2012 18 of 18 integrated device technology ADC0804S030/040/050 single 8 bits adc, up to 30 mhz, 40 mhz or 50 mhz 16. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4 quick reference data . . . . . . . . . . . . . . . . . . . . . 2 5 ordering information . . . . . . . . . . . . . . . . . . . . . 2 6 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 7 pinning information . . . . . . . . . . . . . . . . . . . . . . 4 7.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 7.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 8 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 9 thermal characteristics . . . . . . . . . . . . . . . . . . 5 10 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 6 11 additional informa tion relating to table 6 . . 10 12 application information . . . . . . . . . . . . . . . . . 15 12.1 alternative parts . . . . . . . . . . . . . . . . . . . . . . . 15 13 package outline. . . . . . . . . . . . . . . . . . . . . . . . 16 14 revision history . . . . . . . . . . . . . . . . . . . . . . . 17 15 contact information . . . . . . . . . . . . . . . . . . . . 17 16 contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

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